How to Use Nanosurf easyPLL Plus with Hardware Simulation for Accurate PLL Testing

Step-by-step Nanosurf easyPLL Plus hardware simulation tutorial

1. Goal

Simulate the easyPLL Plus hardware loop to verify lock behavior, tune parameters, and validate control signals before connecting a physical PLL.

2. Required tools & files

• Nanosurf easyPLL Plus control software (installed)
• Hardware simulation module or circuit model provided by Nanosurf (SPICE netlist or built-in simulator)
• PC with data acquisition / virtual instrument drivers as required
• Example configuration file or baseline settings from the device manual
• Oscilloscope or waveform viewer (software or hardware) for inspecting signals

3. Basic setup

1. Open the easyPLL Plus control application.
2. Select the project or create a new session named “HW‑Sim”.
3. Load the hardware simulation model:
   • If built-in: choose the provided hardware simulation option.
   • If external SPICE/netlist: import the netlist/model file into the simulator panel.
4. Configure signal routing so the PLL controller’s output feeds the simulated VCO input and the simulated VCO output returns to the phase detector input.

4. Initial parameter choices (reasonable defaults)

• Reference frequency: 10 MHz (adjust to your target)
• VCO center frequency: match reference × desired division ratio
• Loop bandwidth: 1–10 kHz (start narrow, widen if lock too slow)
• Phase detector gain: default from model
• VCO sensitivity (Kv): from model datasheet (e.g., 10 MHz/V)
• Loop filter: second-order active or passive prototype — start with a type-II PI or lead-lag with moderate damping (ζ ≈ 0.7)

5. Run open-loop checks

1. With loop open, inject a small reference tone and observe VCO output vs control voltage.
2. Verify VCO sensitivity (Hz/V) by applying a stepped control voltage and measuring frequency shift.
3. Check phase detector output for expected polarity and amplitude.

6. Close the loop in simulation

1. Enable the feedback path in the simulator.
2. Start with conservative loop gain (reduce PD or VCO gain in software).
3. Step the reference frequency or phase and observe time-domain locking behavior.

7. Observe and measure

• Time to lock: measure from step to steady-state phase/frequency.
• Overshoot and ringing: adjust damping via loop filter components.
• Steady-state phase error: confirm meets system spec.
• Control voltage range: ensure it stays within simulated VCO tuning range.
• Noise/phase noise: run long-term simulation and compute phase noise or jitter if simulator supports it.

8. Tuning procedure

1. If lock is slow: increase loop bandwidth or gain incrementally.
2. If overshoot/oscillation: add damping (increase filter R or modify pole/zero locations).
3. If steady-state error too large: adjust loop type or increase integrator action (for type-II).
4. Monitor control voltage headroom; reduce gain if hitting rails.

9. Edge cases & failure modes to test

• Large step in reference frequency (check reacquisition).
• Sudden loss of reference (validate hold/holdover behavior).
• VCO tuning range exceeded (verify flagging or safe behavior).
• Sensor or ADC quantization/noise effects (inject quantization/noise sources).

10. Save & export

• Save tuned parameter set as a configuration/profile.
• Export waveforms, lock metrics, and plots for documentation.

11. Transfer to hardware

• Apply the saved configuration to the physical easyPLL Plus.
• Start with lower gain than simulation, then carefully match behavior while monitoring control voltage and phase detector outputs.

If you want, I can generate an example set of loop‑filter component values and simulated response plots for a specific reference/VCO frequency pair — tell me the reference frequency and VCO Kv.